[libpc] Producer/Consumer vs Reader/Writer
Michael Gerlek
mpg at flaxen.com
Sat Mar 5 14:39:39 EST 2011
Ah yes, Feeble Brain Syndrome -- I know it well.
A Reader is a Producer, a Writer is a Consumer, and a Filter is both a
P and a C. This makes me think about renaming the classes, since P
and C are more suggestive. (I did think about Source and Sink, too.)
Would it be worth it to take on multiple inheritance to make a filter
be a class that sports both a P and a C interface?
Your mental model is correct, and random access for the 2nd phase of
the chipping process is indeed going to be painful (as it presumably
is in liblas too?). A relatively simple caching filter would go a long
way here, I think, and I could write you something simple on Monday...
But really the chipper wants a data source that has already been
indexed. I almost think the 1st phase of the chipper, where it does
all the sequential point reading, should include an index-creating
stage almost as a side-effect?
[I'm in bed today again with my heading pad, but am reading a book on
C++ template programming. Powerful stuff. Will it help with the
PointData model, a la PCL? Dunno yet...]
.mpg
On Mar 5, 2011, at 11:20 AM, Howard Butler <hobu.inc at gmail.com> wrote:
> Michael,
>
> I am working on creating a writer for OCI and running into some dissonance which I'm sure is my feeble brain's fault. Here's what has to happen...
>
> Read data from a Reader (LAS, text, etc) -> reorganize data via Chipper into "blocks" -> write blocks into Oracle by reading reorganized data.
>
> Given the current model, and what I've done so far for the chipper, what are the big picture relationships that need to happen? Is there stuff that's not going to fit so well?
>
> A couple of questions:
>
> - Does Producer == Reader and Consumer == Writer more accurately describe the relationship and intent of these objects?
> - How can the writer reasonably perform random reads into the data? Should the Chipper hook up a cache stage somehow to reorganize the data into the blocks and memory cache it?
>
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